It is known within the field of integrated circuit memories to provide redundant memory rows and redundant memory columns within arrays of memory cells. In this way, should a defect arise which renders a row inoperative or a column inoperative, then one of the redundant rows or column may be functionally substituted for the row or column in which the defect has arisen. This type of redundancy mechanism is becoming increasingly important as process geometries scale to smaller sizes and defects within integrated circuits become statistically more likely. In this context, such redundancy mechanisms are important in maintaining a satisfactory yield.
A problem with redundancy architectures is that they represent an additional overhead in terms of circuit area, power consumption, complexity, and timing which has to be carried by every integrated circuit irrespective of whether or not the redundancy mechanisms for that integrated circuit are needed within the particular instance. For this reason, it is desirable to reduce the overheads associated with such redundancy mechanisms, whilst preserving their ability to maintain a satisfactory yield of properly functioning integrated circuits.
One known form of row redundancy mechanism is to provide redundant rows in each memory bank, each memory bank comprising an array of memory cells. The redundant rows within each memory bank can serve as a functional replacement for any defective rows within that memory bank. It is difficult to decide the number of redundant rows which should be provided in each memory bank. If the number is too small, then there may be insufficient redundant rows to repair all the defective rows which occur within a particular memory bank. This is particularly the case as errors tend to cluster together. However, if too many redundant rows are provided in each memory bank, then this represents an unnecessarily high overhead. Another known approach is to provide a complete bank of redundant rows which can be substituted in place of any of the rows within other banks which may be found to be defective. This approach suffers from the disadvantage that the separate bank of redundant rows has to be provided with its own decoders and other support circuitry and this represents a disadvantageous additional overhead.
As previously discussed, an integrated circuit memory can also suffer from defective columns of memory cells. In order to address this problem it is known to provide redundant columns of memory cells and multiplexers which serve to select the group of columns from which a particular bit of data is to be drawn in dependence upon the memory address with these multiplexers being double the normal multiplexer width such that either an original group of bit lines may be selected or an alternative shifted group of bit lines selected if the original contains a defective column. In this way, the columns of memory cells being utilized to store a given bit to one side of a defective column are all shifted to the side by the multiplexer width being employed within the group of columns. The provision of a full multiplexer width group of columns that can be used as a substitute when a defective column is encountered is disadvantageous in terms of the circuit overhead consumed.